From 797656b1fd368b97e77a468b79505ebabf1c7b7c Mon Sep 17 00:00:00 2001 From: "Paul R. Tagliamonte" Date: Sat, 2 Mar 2013 19:41:55 -0500 Subject: [PATCH] Add some line bits. --- hy/lex/__init__.py | 2 +- hy/lex/machine.py | 13 ++++++++++++- tests/test_lex.py | 13 +++++++++++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/hy/lex/__init__.py b/hy/lex/__init__.py index 5dc52fe..a327f75 100644 --- a/hy/lex/__init__.py +++ b/hy/lex/__init__.py @@ -2,7 +2,7 @@ from hy.lex.machine import Machine from hy.lex.states import Idle, LexException def tokenize(buf): - machine = Machine(Idle, 0, 0) + machine = Machine(Idle, 1, 0) machine.process(buf) if type(machine.state) != Idle: raise LexException("Incomplete Lex.") diff --git a/hy/lex/machine.py b/hy/lex/machine.py index ba8f3eb..dd65e73 100644 --- a/hy/lex/machine.py +++ b/hy/lex/machine.py @@ -31,10 +31,21 @@ class Machine(object): def accept_result(self, state): if state and state.result: - self.nodes.append(state.result) + result = state.result + + result.start_line, result.end_line = (self.start_line, self.line) + result.start_column, result.end_column = (self.start_column, + self.column) + self.nodes.append(result) def process(self, buf): for char in buf: + + self.column += 1 + if char == "\n": + self.line += 1 + self.column = 0 + if self.submachine: self.submachine.process([char]) if type(self.submachine.state) == Idle: diff --git a/tests/test_lex.py b/tests/test_lex.py index 6806d53..fd1c946 100644 --- a/tests/test_lex.py +++ b/tests/test_lex.py @@ -10,10 +10,23 @@ def test_lex_expression_symbols(): objs = tokenize("(foo bar)") assert objs == [HyExpression([HySymbol("foo"), HySymbol("bar")])] + def test_lex_expression_strings(): objs = tokenize("(foo \"bar\")") assert objs == [HyExpression([HySymbol("foo"), HyString("bar")])] + def test_lex_expression_integer(): objs = tokenize("(foo 2)") assert objs == [HyExpression([HySymbol("foo"), HyInteger(2)])] + + +def test_lex_line_counting(): + objs = tokenize("(foo 2)") + entry = objs[0] + + assert entry.start_line == 1 + assert entry.start_column == 1 + + assert entry.end_line == 1 + assert entry.end_column == 7